`timescale 1ns/1ps
`include "code\source\P0\code.v"

module test_Code;

// Input
reg Clk, Reset, Slt, En;

// Output
wire [63: 0] Output0, Output1;

code u_code(
         .Clk (Clk ),
         .Reset (Reset ),
         .Slt (Slt ),
         .En (En ),
         .Output0 (Output0 ),
         .Output1 (Output1 )
     );

parameter Clock_Half = 5;
parameter Clock = 10;
integer i = 0;

initial begin
    $dumpfile("./release/test_Code.vcd");
    $dumpvars(0, test_Code);
end

initial begin
    Slt <= 0;
    En <= 0;
    Reset <= 1;

    #Clock;
    Reset <= 0;
    Slt <= 1;
    En <= 1;

    #(Clock * 3);
    Reset <= 1;

    #(Clock);
    Reset <= 0;
end

initial begin
    Clk <= 0;
    for (i = 0;i < 500;i += 1) begin
       #Clock_Half;
       Clk = ~Clk; 
    end
end

endmodule
